x86/x64, SIMD, #AVX512, "Aha!" moments. I have been writing code since 1986. Budapest, Europe https://instlatx64.github.io/InstLatx64/https://bsky.app/profile/instlatx64.bsky.socialhttps://bsky.app/profile/instlatx64.bsky.social/post/3mucinzfkuk2kGreat article with #Intel die shots: - #PantherLake (4P+8E+4LPE, #CougarCove) - #WildcatLake (2P+4LPE) - #ClearwaterForest (24c #Darkmont) - #GraniteRapids (44c #RedwoodCove) - #SierraForest (152c #Crestmont) https://hardwareand.co/dossiers/cpu/cest-la-fiesta-du-die-shot-chez-intel30 Aug 2026 13:28 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mucinzfkuk2khttps://bsky.app/profile/instlatx64.bsky.social/post/3mu7kvikhvc2b#Intel #18A page: https://www.intel.com/content/www/us/en/foundry/process/18a.html #18A_P #18A_PT [contains quote post or other embedded content]29 Aug 2026 09:30 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mu7kvikhvc2bhttps://bsky.app/profile/instlatx64.bsky.social/post/3mu5pweulmc2y#AMD refreshed the "SEV-TIO Firmware Interface Specification" to 0.92: https://docs.amd.com/v/u/en-US/58271_PUB_0.92_SEV-TIO28 Aug 2026 15:54 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mu5pweulmc2yhttps://bsky.app/profile/instlatx64.bsky.social/post/3mu5pvgbaqk2yThe Queen's Gambit is a very useful series, after which it is much easier to explain what I am doing when it seems like I am not doing anything. https://www.imdb.com/title/tt10048342/28 Aug 2026 15:54 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mu5pvgbaqk2yhttps://bsky.app/profile/instlatx64.bsky.social/post/3mu52ayyb3c2p#AMD refreshed the "SEV Secure Nested Paging Firmware ABI Specification" to v1.59: https://docs.amd.com/v/u/en-US/56860_PUB_1.59_SEV_SNP #SEV [contains quote post or other embedded content]28 Aug 2026 09:26 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mu52ayyb3c2phttps://bsky.app/profile/instlatx64.bsky.social/post/3mtyuz3v4sk23#Intel released the HotChips 2026 conference #CrescentIsland presentation: https://cdrdv2-public.intel.com/926893/Crescent%20Island%20GPU%20Hot%20Chips%202026.pdf [contains quote post or other embedded content]26 Aug 2026 17:42 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mtyuz3v4sk23https://bsky.app/profile/instlatx64.bsky.social/post/3mty2hkrae22b#Intel released the HotChips 2026 conference #DiamondRapids presentation: https://cdrdv2-public.intel.com/926846/diamond-rapids-hot-chips-2026-keynote-presentation.pdf #APX #AMX #AVX10 #PantherCove26 Aug 2026 09:47 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mty2hkrae22bhttps://bsky.app/profile/instlatx64.bsky.social/post/3mtxzmbupjs2g#Intel refreshed the Advanced Performance Extensions (#Intel #APX) Architecture Specification to 9.0: https://cdrdv2-public.intel.com/926860/355828-009-intel-apx-arch-spec.pdf #APX #DiamondRapids #NovaLake #PantherCove #CoyoteCove #ArcticWolf [contains quote post or other embedded content]26 Aug 2026 09:32 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mtxzmbupjs2ghttps://bsky.app/profile/instlatx64.bsky.social/post/3mtxz2xdwjk2x#Intel refreshed the "Intel® Trust Domain CPU Architectural Extensions" 343754 pdf to 3.0: https://cdrdv2-public.intel.com/733582/343754-003-intel-trust-domain-cpu-architectural-extensions.pdf [contains quote post or other embedded content]26 Aug 2026 09:22 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mtxz2xdwjk2xhttps://bsky.app/profile/instlatx64.bsky.social/post/3mtu3hhyfac2nGood to see that VS18.9 can now disassemble #APX code #VisualStudio2026 [contains quote post or other embedded content]24 Aug 2026 19:54 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mtu3hhyfac2nhttps://bsky.app/profile/instlatx64.bsky.social/post/3mtqum4rvbk2yHow safe is it to assume that if #APX is supported, then #SERIALIZE is too? #Intel #AMD #Zen7 #Zen823 Aug 2026 13:13 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mtqum4rvbk2yhttps://bsky.app/profile/instlatx64.bsky.social/post/3mthn4pnlms2s#AMD #Zen topology refresh with #Snowmass #Zen7 CCD #Zen #Zen2 #Zen3 #Zen4 #Zen5 #Zen6 [contains quote post or other embedded content]19 Aug 2026 21:06 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mthn4pnlms2shttps://bsky.app/profile/instlatx64.bsky.social/post/3mthm756vsc2lThe x86 Ecosystem Advisory Group refreshed the #ACE (AI Compute Extensions) specification v1.16.2: https://x86ecosystem.org/wp-content/uploads/2026/06/ACE_v1_Specification_public.pdf #EAG #Intel #AMD #Zen7 #CoralRapids #AVX512 #AVX10 #AMX [contains quote post or other embedded content]19 Aug 2026 20:49 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mthm756vsc2lhttps://bsky.app/profile/instlatx64.bsky.social/post/3mthlmcgfes2lI converted the #AMD #Zen6c #Monarch CCD configurations to a more conventional 4x8 layout. I still find it hard to believe that a 32-core chip made with a brand new process doesn't have redundant cores. [contains quote post or other embedded content]19 Aug 2026 20:38 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mthlmcgfes2lhttps://bsky.app/profile/instlatx64.bsky.social/post/3mthkparlhk2lInteresting post from the Linux kernel list: According to Christian Ludloff (sandpile.org), neither #AMX_TF32 nor #AMX_TRANSPOSE are completely dead. https://lore.kernel.org/lkml/CAKSQd8V=wfVrUxeU+fDRgKJBLdiyCkkY2SRY+OoRBNE68LFnCg@mail.gmail.com/ [contains quote post or other embedded content]19 Aug 2026 20:22 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mthkparlhk2lhttps://bsky.app/profile/instlatx64.bsky.social/post/3mt6ukfu5tk2uThere are already two working #NovaLake CPUID 300F15 among the #Intel test machines: - 24c/24t 3400 MHz [1] - 28c/28t 3200 MHz [2] #CoyoteCove #ArcticWolf #AVX512 #APX enabled [1]: https://intel-gfx-ci.01.org/tree/drm-xe-fixes/xe-fixes-259-ef526d122b62af5afa437f095aa6661a953676c4/bat-nvls-1/boot0.txt [2]: https://intel-gfx-ci.01.org/tree/drm-xe-fixes/xe-fixes-259-ef526d122b62af5afa437f095aa6661a953676c4/bat-nvls-2/boot0.txt [contains quote post or other embedded content]16 Aug 2026 09:25 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mt6ukfu5tk2uhttps://bsky.app/profile/instlatx64.bsky.social/post/3msaimctdbc2p#Intel released the SDE 10.13.1 (Software Development Emulator) with x86 EAG #ACE (Al Compute Extensions) support: https://www.intel.com/content/www/us/en/download/684897/intel-software-development-emulator.html #NovaLake #DiamondRapids #APX #AVX10_2 [contains quote post or other embedded content]04 Aug 2026 07:31 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3msaimctdbc2phttps://bsky.app/profile/instlatx64.bsky.social/post/3ms45zry5tk2d#AMD [1]: - #Zen8 EPYC: Ravenna - #Zen7 EPYC: -- for AI host Ferrara -- for Agentic Sandbox Fidenza - #Zen6 [2], [3]: -- desktop #OlympicRidge B80F80 #AM5 -- mobile #Medusa1 B80F00 AM5/FP10 -- mobile #Medusa2 BE0F00 #FP10 #Intel - #GriffinCove for RZL [4] - #CopperShark [5] - #ThunderHawk [6] 1/3 [contains quote post or other embedded content]02 Aug 2026 14:11 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3ms45zry5tk2dhttps://bsky.app/profile/instlatx64.bsky.social/post/3ms43wnbhjc2tdocs.amd.com has now officially revealed that - #Medusa1 is FP10/AM5 - #Medusa2 is FP10 - #OlympicRidge is AM5 #Zen6 #Zen6c https://docs.amd.com/search/all?content-lang=en-US [contains quote post or other embedded content]02 Aug 2026 13:33 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3ms43wnbhjc2thttps://bsky.app/profile/instlatx64.bsky.social/post/3ms2d7y7ftk2zIt's really hard to let go of this 3x11 #Zen6c #Monarch CCD configuration idea, because it simply explains the unusual number of cores in CCDs by disabling rows and columns. Okay, that's not great for L3 latency, but I think something similar is needed for the risk of the brand new TSMC N2 process.01 Aug 2026 20:39 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3ms2d7y7ftk2zhttps://bsky.app/profile/instlatx64.bsky.social/post/3mrz43nohi22o#AMD refreshed the "Smart Data Cache Injection (SDCI)" White Paper 58725 to v1.05: https://docs.amd.com/v/u/en-US/58725_1.05_SDCI_White_Paper [contains quote post or other embedded content]01 Aug 2026 08:58 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mrz43nohi22ohttps://bsky.app/profile/instlatx64.bsky.social/post/3mrz2fnxbzk2o#AMD released the "#CDNA5 Instruction Set Architecture Reference Guide" pdf: https://www.amd.com/content/dam/amd/en/documents/instinct-tech-docs/instruction-set-architectures/amd-instinct-cdna5-instruction-set-architecture.pdf [contains quote post or other embedded content]01 Aug 2026 08:28 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mrz2fnxbzk2ohttps://bsky.app/profile/instlatx64.bsky.social/post/3mrx3f45qe22dUnfortunately, the Perfmon counters of the #Intel #NovaLake INT cluster inherited the grouped nature from the older *Coves with a central scheduler, so the number of ports used here is unknown (except for the 3 JEUs). [contains quote post or other embedded content]31 Jul 2026 13:40 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mrx3f45qe22dhttps://bsky.app/profile/instlatx64.bsky.social/post/3mrwu7fxrjs2zA new feature was mentioned for #Intel #CoralRapids on the Linux kernel mailing list: APIC timer virtualization https://lore.kernel.org/lkml/amnPFlSvI3k95uCV@intel.com/ [contains quote post or other embedded content]31 Jul 2026 11:32 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mrwu7fxrjs2zhttps://bsky.app/profile/instlatx64.bsky.social/post/3mrwrhzvirk2k#AMD -- desktop #OlympicRidge CPUID is B80F80 -- mobile #Medusa2 CPUID is BE0F00 https://lore.kernel.org/platform-driver-x86/20260729164034.1331375-1-muralidhara.mk@amd.com/ [contains quote post or other embedded content]31 Jul 2026 10:43 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mrwrhzvirk2khttps://bsky.app/profile/instlatx64.bsky.social/post/3mrwp5hdos22w#AMD refreshed the "AMD64 Architecture Programmer's Manual, Volumes 1-5" 40332 to 4.10, all-in-one: Vol1 24592-Rev. 3.25-May 2026 Vol2 24593-Rev. 3.45-Jul 2026 Vol3 24594-Rev. 3.38-Jul 2026 Vol4 26568-Rev. 3.27-Jul 2026 Vol5 26569-Rev. 3.16-Nov 2021 https://docs.amd.com/v/u/en-US/40332_4.10_APM_Vol1-5 [contains quote post or other embedded content]31 Jul 2026 10:01 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mrwp5hdos22whttps://bsky.app/profile/instlatx64.bsky.social/post/3mrshlr73lc2xInstLatX64 refresh: #Intel: - 2C+4c #Core 7 350, Core 5 320 #WildcatLake D0651 CPUID dump GitHub: https://github.com/InstLatx64/InstLatx64/blob/master/GenuineIntel/GenuineIntel00D0651_WildcatLake_02_CPUID.txt [contains quote post or other embedded content]29 Jul 2026 17:35 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mrshlr73lc2xhttps://bsky.app/profile/instlatx64.bsky.social/post/3mrq37crms222My attempt to assign CCD types on 6th Gen #AMD #EPYC SKUs #Zen6 #Monarch #Powderhorn #Morpheus [contains quote post or other embedded content]28 Jul 2026 18:48 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mrq37crms222https://bsky.app/profile/instlatx64.bsky.social/post/3mrcybxl43s2aUntil the 84-core #AMD #Sorano #EPYC 8635P came to mind (12 CCD x 7-core), this 176-core (8 CCD x 22-core) #Zen6c seemed completely incomprehensible without a 3rd CCD type. But supposing 11x3 core within the #Monarch CCD makes this a yield optimization. https://blogs.microsoft.com/blog/2026/07/20/microsoft-expands-azure-ai-and-hpc-infrastructure-with-amd/ [contains quote post or other embedded content]23 Jul 2026 13:52 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mrcybxl43s2ahttps://bsky.app/profile/instlatx64.bsky.social/post/3mqwwkypp622fInstLatX64 refresh: #Intel - #WildCatLake D0651 [1] - #ClearwaterForest D06D1 [2] - #Xeon 658X 24-Core #GraniteRapids A06D1 CPUID dump - Xeon 6315P #RaptorLake B0671 CPUID dump GitHub: https://github.com/InstLatx64/InstLatx64/commit/ae88464b1b88e364579083ff4445acd505ead471 1/2 [contains quote post or other embedded content]18 Jul 2026 18:49 +0000at://did:plc:c7wfpgmau2a75lzcdgwefndf/app.bsky.feed.post/3mqwwkypp622f