Exploring the ASIC lore. Not your typical lobste. rs link-dumper or book-cover–posting zombie.https://bsky.app/profile/rohan-devarc.bsky.socialhttps://bsky.app/profile/rohan-devarc.bsky.social/post/3mqzzgzhd6c26have you seen god?20 Jul 2026 00:18 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mqzzgzhd6c26https://bsky.app/profile/rohan-devarc.bsky.social/post/3mogjz22x2k26Had fun doing bring up for XC2064, the first FPGA ever made with 64 CLBs. Scale is so small that, I was able to use Logic Cell Array editor to manually place and route the design by hand, no automation.16 Jun 2026 19:31 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mogjz22x2k26https://bsky.app/profile/rohan-devarc.bsky.social/post/3mo67viti2s2rsovereign AI was a scam New Internet was a scam Web3 was a scam AGI by 2025 was a scam resistors are real MIM cap is real transistors are real kT/C noise is eternal Kirchhoff never lied to you parasitic capacitance will outlive your startup13 Jun 2026 12:09 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mo67viti2s2rhttps://bsky.app/profile/rohan-devarc.bsky.social/post/3mml2fwlvmk23Why stop at verilog gaming? Everything from sprites, controller and character animation is a state machine in itself. Now imagine putting a whole rasterization pipeline in there. [contains quote post or other embedded content]24 May 2026 03:45 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mml2fwlvmk23https://bsky.app/profile/rohan-devarc.bsky.social/post/3mivabsnyjk2bWant to play? 😋 Made with verilog.07 Apr 2026 07:16 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mivabsnyjk2bhttps://bsky.app/profile/rohan-devarc.bsky.social/post/3milxnjch4k25So this one guy submitted a very cool entry for @tinytapeout.com's demoscene competition. I really liked the gradient and banner and whole starry sky implemented with LFSR. It's crazy that we can put all of this in one or two tiles.03 Apr 2026 14:47 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3milxnjch4k25https://bsky.app/profile/rohan-devarc.bsky.social/post/3mhye4r4urs2ocooking an asic for demoscene competition 🤘 @tinytapeout.com26 Mar 2026 19:37 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mhye4r4urs2ohttps://bsky.app/profile/rohan-devarc.bsky.social/post/3mganbz2izk2wThese are bare dies of the Kintex-7 XC7K325T and its pin-compatible Chinese clone, the JFM7K325T from Fudan Micro. Only difference is that GTX transceivers of JFM7K325T behave differently, so the xilinx pcie core wouldn't work by default.04 Mar 2026 15:52 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mganbz2izk2whttps://bsky.app/profile/rohan-devarc.bsky.social/post/3mfvjrrpa5k2yANTHROPIC !!!! 👏👏28 Feb 2026 05:50 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mfvjrrpa5k2yhttps://bsky.app/profile/rohan-devarc.bsky.social/post/3mfcrhl3kgs2fBREAKING TRUMP ANNOUNCES MAGAS WILL BECOME 10% MORE STUPID & BELOW THE AVERAGE IQ.20 Feb 2026 18:47 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mfcrhl3kgs2fhttps://bsky.app/profile/rohan-devarc.bsky.social/post/3mcxbrffavs2aFly through video for ROM-less Cordic Engine design. This design is on TTSKY25A shuttle by @tinytapeout.com Made easy with BlenderGDS plugin - https://github.com/aesc-silicon/BlenderGDS @mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social21 Jan 2026 18:17 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mcxbrffavs2ahttps://bsky.app/profile/rohan-devarc.bsky.social/post/3mcxbrffavs2aFly through video for ROM-less Cordic Engine design. This design is on TTSKY25A shuttle by @tinytapeout.com Made easy with BlenderGDS plugin - https://github.com/aesc-silicon/BlenderGDS @mattvenn.net @urishaked.bsky.social @aksharvastarpara.bsky.social21 Jan 2026 18:17 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mcxbrffavs2ahttps://bsky.app/profile/rohan-devarc.bsky.social/post/3mchype3zes2aYes, that’s a GDSII render. Yes, it’s inside Blender. Yes, it’s our design on TTSKY25A chip. @tinytapeout.com @mattvenn.net @urishaked.bsky.social15 Jan 2026 16:25 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3mchype3zes2ahttps://bsky.app/profile/rohan-devarc.bsky.social/post/3m4a66tkz7s2jThis is the DCJ11 PDP-11 processor, built using the old-school ZMOS tech, a 3  μm NMOS process with two interconnect layers. It was one of the first NMOS processes to use separate metal layers for local connections and global signals.28 Oct 2025 05:10 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3m4a66tkz7s2jhttps://bsky.app/profile/rohan-devarc.bsky.social/post/3m445mhulzc26This looks like a matrix. Each one has 128 analog switches. We can do 8x16 analog array with one. So this is actually a analog matrix.26 Oct 2025 14:49 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3m445mhulzc26https://bsky.app/profile/rohan-devarc.bsky.social/post/3m3dmdrohp22wGoogle has open sourced its Coral NPU, which uses a 32 bit RISC V core with the Zve32x extension. It supports vector arithmetic on data ≤ 32 bits, making it great for DSP applications. It has been prototyped on a Xilinx Ultrascale Plus FPGA platform. https://github.com/google-coral/coralnpu16 Oct 2025 20:36 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3m3dmdrohp22whttps://bsky.app/profile/rohan-devarc.bsky.social/post/3lzvctmc7as2wFYI : Original electronic diary was invented by a Indian guy known as Satyan Pitroda, alias Sam Pitroda. He may be a tad racist, but a great guy. I mean all Indians are racist to each other, who cares. https://www.computerhistory.org/revolution/mobile-computing/18/318/1716 [contains quote post or other embedded content]28 Sep 2025 10:44 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3lzvctmc7as2whttps://bsky.app/profile/rohan-devarc.bsky.social/post/3ly5qg7tsvk2aLow power math within few clock cycles. Imagine it, then put it into silicon. Made by Vicharak aka @aksharvastarpara.bsky.social 's team and two FPGA freaks. Check - t.co/vBGGA2i0uX Thanks @mattvenn.net and @urishaked.bsky.social and whole @tinytapeout.com team for making this possible.06 Sep 2025 08:18 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3ly5qg7tsvk2ahttps://bsky.app/profile/rohan-devarc.bsky.social/post/3lw2awhyass2cSPI-slave device for seven-segment display on TT base board. TT FPGA controls seven-segment display via spi-slave and the RP2040 just sends it a 6-bit message to light up the LEDs.10 Aug 2025 12:12 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3lw2awhyass2chttps://bsky.app/profile/rohan-devarc.bsky.social/post/3lvo4ngkx7c2fASICs are cool. FPGAs are ❤️. FPGA brother to tinytapeout ASIC by Michael Bell aka @rebelmike.bsky.social @tinytapeout.com @mattvenn.net @urishaked.bsky.social05 Aug 2025 16:23 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3lvo4ngkx7c2fhttps://bsky.app/profile/rohan-devarc.bsky.social/post/3lvmchld6oc2lDefinitely true!04 Aug 2025 23:02 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3lvmchld6oc2lhttps://bsky.app/profile/rohan-devarc.bsky.social/post/3luzqwzrpgk2uEvening chai is hot enough to give the FPGA a first-class ticket to the electronic afterlife.28 Jul 2025 14:01 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3luzqwzrpgk2uhttps://bsky.app/profile/rohan-devarc.bsky.social/post/3luxcilupj22tWhen man craves for aesthetics, he craves for God...and good quality probes.27 Jul 2025 14:37 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3luxcilupj22thttps://bsky.app/profile/rohan-devarc.bsky.social/post/3luif2lacbs24It looks good. Got the power led. Now trying to get it to work as intended. [contains quote post or other embedded content]21 Jul 2025 16:13 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3luif2lacbs24https://bsky.app/profile/rohan-devarc.bsky.social/post/3lubbf4gm722xBooted KianV uLinux from Hirosh on TinyTapeout ASIC.18 Jul 2025 20:19 +0000at://did:plc:x2j5bio34s2the6uh3ygr7nt/app.bsky.feed.post/3lubbf4gm722x